Matrix Methods for the Dynamic Range Optimization of Continuous-TimeGm-CFilters

This paper presents a synthesis procedure for the optimization of the dynamic range of continuous-time fully differential G m - C filters. Such procedure builds up on a general extended state-space system representation which provides simple matrix algebra mechanisms to evaluate the noise and distortion performances of filters, as well as, the effect of amplitude and impedance scaling operations. Using these methods, an analytical technique for the dynamic range optimization of weakly nonlinear G m - C filters under power dissipation constraints is presented. The procedure is first explained for general filter structures and then illustrated with a simple biquadratic section

A 0.18 μm CMOS low noise, highly linear continuous-time seventh-order elliptic low-pass filter

This paper presents a fast procedure for the system-level evaluation of noise and distortion in continuous-time integrated filters. The presented approach is based on Volterra's series theory and matrix algebra manipulation. This procedure has been integrated in a constrained optimization routine to improve the dynamic range of the filter while keeping the area and power consumption at a minimum. The proposed approach is demonstrated with the design, from system- to physical-level, of a seventh-order low-pass continuous-time elliptic filter for a high-performance broadband power-line communication receiver. The filter shows a nominal cut-off frequency of fc = 34MHz, less than 1dB ripple in the pass-band, and a maximum stop-band rejection of 65dB. Additionally, the filter features 12dB programmable boost in the pass-band to counteract high frequency components attenuation. Taking into account its wideband transfer characteristic, the filter has been implemented using G m-C techniques. The basic building block of its structure, the transconductor, uses a source degeneration topology with local feedback for linearity improving and shows a worst-case intermodulation distortion of -70 dB for two tones close to the passband edge, separated by 1MHz, with 70mV of amplitude. The filter combines very low noise (peak root spectral noise density below 56nV/√Hz) and high linearity (more than 64dB of MTPR for a DMT signal of 0.5Vpp amplitude) properties. The filter has been designed in a 0.18μm CMOS technology and it is compliant with industrial operation conditions (-40 to 85°C temperature variation and ±5% power supply deviation). The filter occupies 13mm2 and exhibits a typical power consumption of 450 mW from a 1.8V voltage supply.Ministerio de Ciencia y Tecnología TIC2003-0235

A 0.18μm CMOS low-noise elliptic low-pass continuous-time filter

This paper presents a seventh order low-pass continuous-time elliptic filter for use in a high-performance wireline communication receiver. As an additional attribute, the filter provides programmable boost in the pass-band to counteract high frequency components attenuation. The filter shows a nominal cutoff frequency of fc=34 MHz , less than 1dB ripple in the pass-band, and a maximum stop-band rejection of 65dB. The filter also exhibits low noise feature (peak root spectral noise density below 56nV√Hz) and high linearity (more than 64dB of MTPR for a DMT signal of 0.5Vpp amplitude). It has been designed in a 0.18μm CMOS technology and it is compliant with industrial operation conditions (-40 to 85° C temperature variation and ± 5% power supply deviation). Simulations show a typical power consumption of 450 mW @ 1.8V supply.Ministerio de Ciencia y Tecnología TIC2003-0235

System-level optimization of baseband filters for communication applications

In this paper, a design approach for the high-level synthesis of programmable continuous-time baseband filters able to achieve optimum trade-off among dynamic range, distortion behavior, mismatch tolerance and power area consumptions is presented. The proposed approach relies on building programming circuit elements as arrays of switchable unit cells and defines the synthesis as a constrained optimization problem with both continuous and discrete variables, this last representing the number of enabled cells of the arrays at each configuration. The cost function under optimization is, then, defined as a weighted combination of performance indices which are estimated from macromodels of the circuit elements. The methodology has been implemented in MATLAB™ and C++, and covers all the classical approximation techniques for filters, most common circuit topologies (namely, ladder simulation and cascaded biquad realizations) and both transconductance-C (Gm-C) and active-RC implementation approaches. The proposed synthesis strategy is illustrated with a programmable equal-ripple ladder Gm-C filter for a multi-band power-line communication modem.P.R.O.F.I.T. FIT-070000-2001-84

Comparison of the DR of continuous time Gm-C filters using different structures

Comunicación presentada al "ICC'06" celebrada en Atenas del 10 al 12 de Julio del 2006.This paper presents design techniques to evaluate the noise and distortion of continuous time Gm-C filters. Also presents techniques to improve the dynamic range of such filters keeping a relation of integer numbers between the transconductors. Furthermore the comparison of the dynamic range for the same power using different structures is presented.This work has been partially funded by the Spanish MCyT under Project TIC2003-02355 (RAICONIF).Peer Reviewe

Comparison of the DR of continuous time Gm-C filters using different structures

This paper presents design techniques to evaluate the noise and distortion of continuous time Gm-C filters. Also presents techniques to improve the dynamic range of such filters keeping a relation of integer numbers between the transconductors. Furthermore the comparison of the dynamic range for the same power using different structures is presented

Matrix methods for the dynamic range optimization of continuous-time Gm-C filters

This paper presents a synthesis procedure for the optimization of the dynamic range of continuous-time fully differential Gm-C filters. Such procedure builds up on a general extended state-space system representation which provides simple matrix algebra mechanisms to evaluate the noise and distortion performances of filters, as well as, the effect of amplitude and impedance scaling operations. Using these methods, an analytical technique for the dynamic range optimization of weakly nonlinear Gm-C filters under power dissipation constraints is presented. The procedure is first explained for general filter structures and then illustrated with a simple biquadratic section. © 2008 IEEE.Peer Reviewe

A 0.13μm CMOS Current Steering D/A Converter for PLC and VDSL Applications

This paper describes the design of a 12-bit 80MS/s Digital-to-Analog converter implemented in a 0.13μm CMOS logic technology. The design has been computer-aided by a developed toolbox for the simulation and verification of Nyquist-Rate Analog-to-Digital and Digital-to-Analog converters in MATLAB. The converter is segmented in an unary current-cell matrix for 8 MSB's and a binary-weighted array for 4 LSB's. Current sources of the converter are laid out separately from current-cell switching matrix core block and distributed in double centroid to reduce random errors and transient noise coupling. The linearity errors caused by remaining gradient errors are reduced by a modified Q2 Random-Walk switching sequence. Transistor-level simulation results show that the Spurious-Free Dynamic-Range is better than 58.5dB up to 80MS/s. The estimated Signal-to-Noise Distortion Ratio yield is 99.7% and better than 58dB from DC to Nyquist frequency. Multi-Tone Power Ratio is higher than 59dB for several DMT test signals. The converter dissipates less than 129mW from a 3.3V supply and occupies less than 1.7mm2 active area.This work has been supported by the MEDEA+ (A110 MIDAS) and TIC2003-02355RAICONIF Projects.Peer reviewe

A 12-bit CMOS Current Steering D/A Converter for Embedded Systems

This paper describes the design of a 12-bit digital-to-analog converter for a wireline modem chip implemented in a 0.13μm digital CMOS technology. Transistor-level simulations from extracted layout at the nominal modem data rate of 8OMS/s show an Spurious-Free Dynamic-Range (SFDR) better than 62dB at Nyquist rate under industrial operation conditions (-40 to 85º temperature range and ±10% supply variations) and for all technology process corners. Additionally, the converter achieves a Multi-Tone Power Ratio (MTPR) higher than 59dB for different Discrete MultiTone (DMT) test patterns consisting of 1536 carriers that fall in the Nyquist band. Simulation results at a higher data rate of 200MS/s are also shown in the paper. The converter dissipates less than 150mW from a mixed 3.3/1.2V supply and occupies less than 1.7mm2.This work has been supported by the MEDEA+ (Al10-MIDAS) and TIC2003-02355 Projects.Peer reviewe

An Embedded 12-bit 80MS/s A/D/A Interface for Power-Line Communications in 0.13μm Pure Digital CMOS Technology

This paper presents an embedded interface, comprising both A/D and D/A converters, which has been implemented in a 0.13μm pure digital CMOS technology. The interface is integrated in a system for high-performance broad-band power-line communications. The A/D converter uses a pipelined structure, whereas the D/A stage is based on segmented current steering techniques. In both cases, specifications are 12-b resolution at 80MS/s and MTPR above 56dB.This work has been partially funded by the European MEDEA+ Office under Project MIDAS-A110.Peer reviewe